A flash memory uses nonvolatile memory elements each having a control gate and a floating gate similar to FAMOSS, as its memory cells, and each memory cell can be constructed of one transistor. In such a flash memory, for a programming operation, the drain voltage of the nonvolatile memory element is set to about 5 V, as shown in FIG. 12, and the word line connected to the control gate is set to about −10 V, so that the charge on the floating gate is drawn therefrom by tunnel current to set the threshold voltage to a low value (logic “0”).
For the erasing operation, as shown in FIG. 13, the P-type semiconductor region pwell is set to about −5 V, and the word line is set to about 10 V, so that tunnel current is caused to flow to inject negative charges into the floating gate, thereby to set the threshold value to a high state (logic “1”). Thus, one memory cell is able to store the data of one bit.
Incidentally, there has been the concept of a so-called “multi-value” has been proposed in which data of two or more bits are stored in one memory cell so as to increase the storage capacity. An invention relating to such a multi-value memory is disclosed in Japanese Patent Laid-Open No. 121696/1984.
In a flash memory of the prior art, it is known that the variation of the threshold value is increased due to both a weak program (the disturb) or the like caused by the programming reading and erasing operations of an adjacent bit and natural leakage (the retention), and consequently, the half-value width (the width of the peak of the bell-shaped variation distribution at the position of a half peak value, as shown in FIG. 3) of the variation distribution of the threshold value corresponding to logic “0” and increases with the lapse of time. The inventors have found that, with the lower level of the power supply voltage of future LSIS, the threshold voltage of the memory cells may exceed the marginal range for the read voltage by the broadening of the variation distribution with time, thereby to cause a malfunction.
This problem is especially serious in a multi-value memory for storing one memory element with data of a plurality of bits by the difference between the threshold values, because this difference is small for the individual data. In a flash memory, moreover, there is a technical problem for minimizing the processing time and the circuit scale intrinsic to the multi-value memory, because of the erasing and program verifying operations intrinsic to the nonvolatile memory device.